Device for changing pitch of an audio signal to improve intelligibility

ABSTRACT

A helium speech decoder of the pitch scaler type is disclosed as including a pair of bucket brigade analog delay lines which are timely loaded with the electrical signal equivalent of human voice signals that are effectively supplied thereto by an electroacoustical transducer. The respective frequencies of signals unloaded by said bucket brigade delay lines are controlled by a pair of clock generators which drive said bucket brigade delay lines at different predetermined frequencies in response to the output signals from oscillator driven Number programmed and decade counters. The timely and alternate loading (and unloading) of said bucket brigade delay lines is effected by a binary counter, the state of which changes periodically in response to the aforesaid Number programmed counter in such manner as to acutate and alternate switch means in order to properly effect the driving of said pair of clock generators and, hence, shift said bucket brigade delay lines at their predetermined respective frequencies, as well as effect the timely unloading thereof in synchronism with the alternation thereof. The unloaded signals from said bucket brigade delay lines are then indicated by any suitable readout apparatus and/or otherwise used by any other compatible utilization apparatus.

United States Patent [191 Dildy, Jr.

aszaisa Aug. 6, 1974 [5 DEVICE FOR CHANGING PITCH OF AN AUDIO SIGNAL TO IMPROVE INTELLIGIBILITY [75] Inventor: Clell A. Dildy,Jr., Panama City,

Fla.

[73] Assignee: The United States of America as represented by the Secretary of the Navy, Washington, DC.

[22] Filed: July 9, 1973 [21] Appl. N0.: 377,878

[52] US. Cl 179/1 SA [51] Int. Cl. G10l l/00 [58] Field of Search..... 179/1 SA, 100.2 K, 15.55 R

[56] References Cited UNITED STATES PATENTS 3,62l,l50 ll/l97l Pappas l79/l5.55T

Primary Examiner-Kathleen H. Claffy Assistant ExaminerTommy P. Chin Attorney, Agent, or FirmRichard S. Sciascia; Don D. Doty; Harvey A. David [57] ABSTRACT A helium speech decoder of the pitch scaler type is disclosed as including a pair of bucket brigade analog delay lines which are timely loaded with the electrical signal equivalent of human voice signals that are effectively supplied thereto by an electroacoustical transducer.

The respective frequencies of signals unloaded by said bucket brigade delay lines are controlled by a pair of clock generators which drive said bucket brigade delay lines at different predetermined frequencies in response to the output signals from oscillator driven Number programmed and decade counters. The timely and alternate loading (and unloading) of said bucket brigade delay lines is effected by a binary counter, the state of which changes periodically in response to the aforesaid Number programmed counter in such manner as to acutate and alternate switch means in order to properly effect the driving of said pair of clock generators and, hence, shift said bucket brigade delay lines at their predetermined respective frequencies, as well as effect the timely unloading thereof in synchronism with the alternation thereof. The unloaded signals from said bucket brigade delay lines are then indicated by any suitable readout apparatus and/or otherwise used by any other compatible utilization apparatus.

19 Claims, 5 Drawing Figures 3 M 6 I I I I I I REAoour j i i /1/ I I IBI/ BUCKET fi GANG I RECORDER I gg 22 ZI I SWITCH I ss I u as 39 (52 em aggE l I I I I COUNTER I S,GNAL EAR I I PROCESSOR PHONES I I2 l9 l \7 (AMP) M 22 I L l I L I l mcaop aco, W43 PHONE q RlA'aiisoR (hili ti ist I ll I UTILIZAT I '-L I APPARATUS 3 l I I I L, l l DECADE BUCKET BRIGADE COUNTER I ra I I MM (slz em I FI- SWITCH I c tiiiiii a INVERTER I 32 NAND I no STAGE) CLOCK I I NAND 27 I I GEN. I I 29 I 'I NAND I I sum 1 or g PATENTED NIB 6 974 r1 I I I l IIL DEVICE FOR CHANGING PITCH OF AN AUDIO SIGNAL TO IMPROVE INTELLIGIBILITY STATEMENT OF GOVERNMENT INTEREST The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

FIELD OF THE INVENTION The present invention relates, in general, to the time compression and expansion of human speech by sampling methods and means and, in particular, is an improved method and means of changing or scaling the pitch of human speech and other signals without changing the syllabic rate, word rate, or other intelligence parameters thereof a deleterious amount. In even greater particularity, the subject invention is a speech decoder which improves the intelligibility of human speech in a helium or helium-oxygen atmosphere, such as those found, for example, in undersea habitats disposed at various and sundry water depths or other ambient environmental pressures that are considerably greater than the earths typical atmospheric pressure.

DESCRIPTION OF THE PRIOR ART Heretofore, several techniques have been employed to expand speech in time. One of the simplest techniques used was to record the speech and then play it back at a speed that was slower than that used for the original recording. Unfortunately, the use of such technique resulted in a decrease in pitch in an amount that was proportional to the difference in record and playback speeds; and of course, if the pitch of the speech were decreased enough to be operative for many practical purposes, the intelligibility thereof was adversely affected, sometimes to the extent that it was useless. Furthermore, communication using such recordplayback techniques could not be accomplished in real time, although it is recognized that the time delay involved could be relaively small, as far as recording and playing back are concerned.

The device of US. Pat. No. 3,621,150, entitled Speech Processor For Changing Voice Pitch, by George W. Pappas purports to make speech of a diver located in a helium-oxygen atmosphere intelligible. In such case, the speech processor thereof makes use of the fact that normal speech may be chopped or segmented at certain rates and still retain its intelligibility. Once segmented into very small pieces, every other piece thereof is discarded and the remaining pieces are recombined. Then the recombined pieces are played back" at a slower speed dependent on the length of the discarded pieces by means of digital shift registers, the number of which may be considerable, and the use of which requires the associated use of analog-to-digital converters at the inputs and outputs thereof, as well as a filter at the output, in order to be effective. Hence, the number of components incorporated therein could be considerable, indeed; and the monetary cost and manufacturing complexities could be prohibitive for most practical purposes.

Other prior art methods and means for processing speech are discussed in the aforementioned patent, but none thereof appear to anticipate or be better than the subject invention. Moreover, neither they nor the speech processors thereof appear to be as effective and as efficient as helium speech decoders as the invention described in detail below.

SUMMARY OF THE INVENTION The instant invention is a speech processing device which renders human speech within a predetermined pressurized helium-oxygen environment such as, for example, that ordinarily existing within a swimmer/- diver undersea habitat, or the like more intelligible than it otherwise would be if it were left in its unnatural, squeaky, Donald Duck-like form. Accordingly, by properly using the subject system, the communications between divers within a pressurized habitat and the communications between undersea divers and surface support people are facilitated.

It is, therefore, an object of this invention to provide an improved pitch scaler.

Another object of this invention is to provide an improved helium speech processor and decoder.

Still another object of this invention is to provide an improved method and means for discretely segmenting, delaying, and reconstructing predetermined portions of acoustical and electrical signals.

A further object of this invention is to provide an improved signal frequency contractor, without adversely affecting the syllabic or word rate thereof to the extent that the data are no longer intelligible or useful.

Another object of this invention is to provide an improved method and means for eliminating the Donald Duck effect from human speech that is spoken in a pressurized helium-oxygen atmosphere, such as, for instance, that which is employed as a life-support atmosphere for divers working and living in deep underwater habitats.

Another object of this invention is to provide an improved method and means for sampling and frequency compressing a speech or other acoustical or electrical signal while restoring the essential pitch characteristics thereof.

Other objects and many of the attendant advantages will be readily appreciated as the subject invention becomes better understood by reference to the following detailed description, when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of a preferred embodiment of the subject invention;

FIG. 2 is a block diagram of another preferred species of the instant invention;

FIG. 3 is an idealized graphical waveform representation of several key operative signals which are produced by several of the components incorporated in the device of FIG. 1;

FIG. 4 is an idealized enlarged view of the signal waveforms which occur between t and of the graphical representation of FIG. 3; and

FIG. 5 graphically portrays a simple pure tone sine wave test signal and the discontinuity of electronic splicing thereof effected by the devices of FIGS. 1 and 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a preferred embodiment of the subject invention is shown as including a microphone 11 with the output thereof connected to the input of a signal processor 12 which may include amplitiers, filters, threshholders, and any other components deemed necessary to put the output signal from microphone 11 into a more useful and suitable form. The output from signal processor 12 is connected to the input ofa first 512 bit bucket brigade delay line 13 and to the input of a second 512 bit bucket brigade delay line 14.

Bucket brigade delay lines 13 and 14 are, of course, well known in the art as being analog shift registers and are commercially available from the N. V. Philips Gloeilampensabrieken of Eindohoven, Nederland. Also, bucket brigade delay lines suitable for incorporation in this invention are discussed in the IEEE Journal of Solid-State Circuits, Vol. 804, No. 3, June 1969 issue, in an article therein entitled Bucket-Brigade Electronics New Possibilities for Delay, Time-Axis Conversion and Scanning, at page 131.

The outputs of bucket brigade delay lines 13 and 14 are respectively connected to the inputs of a pair of switches 15 and 16. In actuality, switch 15 is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) 17 of the C4016 AE type manufactured by RCA. Hence, the output of bucket brigade delay line 13 is connected to the drain input of said transistor 17. Also, in actuality, switch 16 is a field effect transistor 18 of the type that is identical to field effect transistor 17, and the drain input thereof is connected to the output of the aforesaid bucket brigade delay line 14.

An adjustable frequency oscillator 19, preferably adjusted so as to produce a 500 Kilocycle per second output signal, has the output thereof connected to the input of a programmable counter 21 which, in turn, has the plurality of inputs thereof connected to the plurality of outputs of a binary coded decimal switch 22 representing a predetermined Number, in this particular instance preferably Number 20. The output of the aforesaid oscillator 19 is also connected to the input of a decade counter 23.

The output of the aforementioned programmable counter 21 is connected to the input of a stage binary counter 24, the output of whichis connected to the input of a logical inverter 25.

The output of the aforementioned programmable counter 21 is also connected to one of the inputs of NAND gates 26 and 27, with the other input of NAND gate 26 connected to the output of the aforesaid inverter 25, and with the other input of NAND gate 27 connected to the output of the aforesaid binary counter 24.

The output of decade counter 23 is connected to one of the inputs of a NAND gate 28 and to one of the inputs of a NAND gate 29, with the other inputs of said NAND gates 28 and 29 connected to the output of the aforesaid binary counter 24 and the output of the aforesaid inverter 25, respectively. The outputs of NAND gates 26 and 28 are connected to the inputs of a NAND gate 31, while the outputs of the aforementioned NAND gates 27 and 29 are connected to the inputs of a NAND gate 32.

As may readily be seen, the particularly disclosed arrangement of NAND gates 26, 28 and 31 constitute an electronic switch 33, and the particular arrangement of NAND gates 27, 29 and 32 constitute an electronic switch 34. Moreover, as may readily be seen, all of the aforementioned switches 15, 16, 33, and 34 constitute an electronic gang switch 35.

The gate of switch transistor 17 is connected to the output of inverter 25, and the gate of switch transistor 18 is connected to the output of the aforesaid binary counter 24. The outputs from switches 15 and 16 are respectively taken from the sources of transistors 17 and 18 and, in this particular instance, are interconnected in such manner as to constitute the data signal output of gang switch 35.

As may readily be seen, the outputs from electronic switches 33 and 34 are taken from the outputs of NAND gates 31 and 32, respectively, and they, in turn, are respectively connected to the frequency control inputs of a pair of clock generators 36 and 37, the outputs of which are respectively connected to the shift in puts of bucket brigade delay lines 13 and 14.

The source outputs of transistors 17 and 18, as previously mentioned, constitute the data signal output of gang switch 35 and, thus, they are interconnected and connected to the input of another signal processor 38 which, may, for example, include suitable amplifiers, filters, and any other electronic components suitable for processing the signals supplied thereto into a more useful form. The output of signal processor 38 is connected to the-input of earphones 39 and/or recorder 41, either one or both of which, in this particular instance, is considered as being a readout 42. Also, the output of signal processor 38 is optionally connected to the input of any appropriate compatible utilization apparatus 43, as desired.

Referring now to FIG. 2, another species of the subject invention is disclosed as including a microphone 51, the output of which is connected to the input of a signal processor 52 which includes an amplifier 53 and may include other signal processing apparatus as well. Since said other signal processing apparatus is not disclosed herein, the output of signal processor 52 is taken from the output of amplifier 53 and is connected to the input of a pair of 512 bit bucket brigade delay lines 54 and 55.

An adjustable but preferably 500 KC per second oscillator 56 has the output thereof connected to the input of a programmable counter 57, the programming inputs of which are connected to the outputs of a binary coded decimal, two decade switch 58 which, in this particular instance, contains the Number 20. Also, the output of the aforesaid oscillator 56 is connected to the input of a decade counter 59. A solenoid actuated gang switch 61 is connected to the outputs of the aforementioned bucket brigade delay lines 54 and 55, as well as to the outputs of the aforesaid programmable counter 57 and decade counter 59 in manners more fully disclosed subsequently.

In this particular instance, said gang switch 61 incorporates a solenoid 62 which is mechanically connected to a trio of single throw-double pole switches 63, 64, and 65 for simultaneous switching action thereof. As shown in FIG. 2, one of the poles 66 of switch 63 is connected to the output of program counter 57, and one of the poles 67 of switch 64 is connected to the output of decade counter 59 as well as to the other pole 68 of the aforesaid switch 63. The other pole 69 of switch 64 is connected to pole 66 of said switch 63. Switch 65 has one of the poles 71 thereof connected to the output of the aforementioned bucket brigade delay line 54, with the other pole 72 thereof connected to the output of the aforesaid bucket brigade delay line 55. The throws of said switches 63 and 64 are respectively connected to the frequency controlled inputs of clock generators 73 and 74, with the outputs thereof, in turn, respectively connected to the shift inputs of the aforementioned bucket brigade delay lines 54 and 55.

The output of programmable counter 57 is also connected to the input of a stage binary counter 75, the output of which is connected to the electrical input of the aforesaid solenoid 62 for timely effecting the actuation thereof and, thus, the timely actuation of the aforementioned gang switch 61. j

The output from gang switch 61 is taken from the throw of switch 65 and is connected through an amplifier 76 to the inputs of earphones 77, a readout 78 if different from the aforementioned earphones 77, and any other suitable utilization apparatus 79 compatible therewith.

Obviously, by comparing the devices of FIGS. 1 and 2, it may readily be seen that they constitute two different species of the same invention, with the differences therebetween essentially involving the particular switching arrangements thereof. Consequently, it may be seen that the species of FIG. 1 employs an electronic switching arrangement in the form of gang switch 35, while the species of FIG. 2 incorporates an electromechanical switching arrangement in the form of gang switch 61. Of course, other minor structural differences are employed, in order to effect the proper operational procedures necessary to the proper functioning of each one thereof.

MODE OF OPERATION The operation of the invention will now be discussed briefly in conjunction with all of the figures of the drawing; however, because the embodiment disclosed in FIG. 1 presently appears to be the more important species of the two species disclosed in FIGS. 1 and 2, it will be used in detail for operational disclosure purposes and supplemented by disclosures of the operational differences which occur in the embodiment of FIG. 2, insofar as so doing is warranted to provide a full and complete disclosure of the operation of the subject invention.

Accordingly, as may readily be seen, if human speech is spoken into microphone 11, the acoustical energy applied thereto will be converted into proportional electrical energy which is further processed to a more useful form such as, for instance, by amplification, filtering, thresholding, or the like by signal processor 12. The more useful output signal from signal processor 12 is then applied to the 512 bit bucket brigade delay lines 13 and 14, each of which is timely activated so as to provide alternate operations thereof by means which will be discussed more fully subsequently.

Because the 512 bit bucket brigade delay lines incorporated in the subject invention as delay lines 13 and 14 are key components of the subject invention and, thus, obviously increase the performance thereof, it would appear, at this time, that a simple discussion thereof is warranted, in order to insure that there is a reasonable understanding of why the subject invention is unique and produces the new and improved results set forth in the above stated objectives.

Until such time as the bucket brigade delay line was invented, the delay of an analog signal in an analog delay line ordinarily proved to be complex and cumbersome, inasmuch as the problem had to be solved, as a general rule, by electromechanical procedures such as magnetic recording and the like. Of course, in theory, LC networks could be used for delay line purposes, but because of the range of memory capacity covered thereby is not optimum for the purposes of this invention, the use thereof is neither desirable nor preferable. Moreover, due to the copious quantities of sections of said LC networks are required thereby, the compact design thereof is not possible, and even more important, distortion accumulates therein at an unacceptable level. Such adverse distortion accumulates therein, by in large, as a result of the incorporation of the inductive elements which tend to deviate in their behavior from an ideal reactive element more so than do capacitors. Of course, said inductive elements are exceedingly difficult to miniaturize. Consequently, when integratedcircuit technology devised an analog shift register employing capacitor type elements as the memory elements without inductive elements being combined therewith, the state of the art of analog delay lines advanced to where they, when included in the subject invention, would constitute a new and unique combination of elements which produce vastly improved results heretofore unobtainable by any prior means.

Bucket brigade delay lines 13 and 14 of FIG. 1 and bucket brigade delay lines 54 and 55 of FIG. 2 constitute the aforementioned new electronic variable delay lines for analog data processing and, thus, as previously suggested, become key factors in the superb performance obtained from this invention. Because the basis therefor is a chain of storage capacitors in chargetransfer circuits which act as an analog shift register with an externally variable shift rate, they have become known as bucket brigade circuits. Information is stored therein in an array of capacitors not directly as charged level but, rather, as a charge deficit. Accordingly, only one transistor per storage capacitor is required, which makes it less complex than the analog delay lines of the prior art.

The bucket brigade delay lines incorporated in this .invention use two complementary clock signals, with a frequency equal to the sampling frequency applied to the input signal. From a performance standpoint, such delay lines allow the interchange between bandwidth and delay within wide limits. Of course, the signal delay which is effected internally therein can, hence, be accurately controlled or changed electronically. Since each storage capacitor thereof is located between the collector and the base of the switching transistor within each stage, an analog delay line so constructed simply acquires the form of a series connection of transistors, each of which has a relatively large parathetic capacitance.

The performance of the bucket brigade type of analog delay line is dependent upon the interconnection and interaction between successive signal samples which travel along the capacitor chain. Therefore, it may be seen that the electrical signal to be delayed therein is sampled and stored in a cascade of capacitors that are interconnected by electronics devices that are actuated at the frequency of the signal sampler. Inasmuch as a new sample cannot be stored in a capacitor before the signal sample existing therein is completely removed, only half the number of capacitors incorporated therein actually store any information at any given instant, with the others thereof being empty at that time.

Because the aforesaid functional operations are performed in bucket brigade delay lines which are made up of transistors and capacitors only, only one transistor is needed for the abovementioned type switching operation. Of course, such would be more readily evident if reference was made to the aforementioned sales and information literature of the Phillip Research Laboratories of Eindohven, Nederland. In any event. it should at least be understood that as the sampling interval is completed, the information is transferred from one odd capacitor to the next odd capacitor by a charge deficit replenishment technique, which, in turn, is most beneficial in the subject invention when it is combined with the other associated and previously described components thereof. The fact that it also results in being an analog shift register which may be controlled electronically instead of being a digital shift register, and the fact that only two thereof are required as a minimum although many thereof may be employed, if so desired instead of a large number of digital shift registers, a considerable savings, both economically and space wise, is effected.

In the device of FIG. 1, the two bucket brigade delay lines 13 and 14 are driven by .a pair of clock generators 36 and 37 in alternation in accordance with the switching arrangement effected by gang switch 35. The condition of the various and sundry switches namely, switches l5, 16, 33, and 34 are caused to be alternated in such manner that the signal frequency from the output of oscillator 19 causes a predetermined frequency signal to be effected by programmable counter 21 as a result of binary coded decimal, two decade switch 22 supplying a predetermined number (N) thereto. The signal output frequency from programma ble counter 21, in turn, enables binary counter 24 in such manner that the polarities of the signals supplied to the respective NAND gates of switches 33 and 34 are effective to supply the control signal of one frequency to clock generator 36 from programmable counter 21 at one-half of the cycle thereof while supplying another frequency signal from decade counter 23 to clock generator 37 during the other half of the cycle. Of course, when the cycles are switched every 512 hits as a result of the running of binary counter 24, that control signal which had previously been supplied to clock generator 36 from programmable counter 21 is now supplied to clock generator 37 and the output signal from decade counter 23 is supplied as the new control signal to clock signal generator 36. In other words, bucket brigade delay line 13 is now clocked from the programmable counter 21. The division ratio of this counter is determined externally by inserting a Number N which, for the purpose of this explanation, is considered to be any integer from to 30, although other numbers may be used. This means that the clock signal applied to clock generator 36 is such as to cause bucket brigade delay line to be clocked between 100 Kilohertz and 33% Kilohertz. It can be seen that the ratio of the two clocks that is clock generators 36 and 37 which are applied to the two bucket brigade delay lines lies between L0 and 3.0, or for example, 1.0, 1.1, 1.2 2.9. and 3.0.

Bucket brigade delay line 13 is effectively connected in this instance through switch to the input of signal processor 38 and, thus, to earphones 39, recorder 41,

readout 42, and/or utilization apparatus 43. It is emptied at a 50 kilohertz rate if the aforesaid number (N) has been chosen to be 20. But after 512 50 kilohertz clock pulses, the 10 bit binary counter 24 changes state. This, in turn, causes switches 15, 16, 33, and 34 to likewise change state, and, as a result thereof, bucket brigade delay line 13 will now be loaded at a kilohertz rate and bucket brigade delay line 14 will be unloaded at a 50 kilohertz rate through switch 18 to signal processor 38 and, thus, to the aforementioned earphone 39, recorder 41, readout 42, and/or utilization apparatus 43. After 512 more 50 kilohertz clock pulses, the process repeats itself. The net result is that all of the voice frequencies applied to the aforementioned microphone 11 which occur above 100 hertz are divided by N divided by It), i.e., in the example above, numeral 2. All frequencies below 50 hertz will remain unchanged and the above stated desired results will have been accomplished.

From the foregoing it should be obvious that the timing of the switches for electronically controlling the frequencies of the bucket brigade delay lines is an important aspect of the subject invention, inasmuch as they effectively control the alternate chopping at a pair of different frequencies of the input signal that is supplied to microphone 11 in order to reduce the pitch of the output signal at, say, earphones 77.

As previously indicated, the switching operation occurring within the invention is exceedingly important; therefore, several of the key waveforms which cause said switching operation to be produced are depicted in FIGS. 3 and 4. Referring first to FIG. 3, FIG. 3(A) illustrates the waveform of the signal which is produced by binary counter 24 over a long time period, and the waveform of FIG. 3(B) is that of the signal produced at the output of inverter 25 over the same time period as that used in conjunction with FIG. 3(A). When a similar time period is employed as the abscissa, as it is in FIG. 3, the signal wave forms pictured in FIG. 3(C) and (D) of FIG. 3 appear to merely be straight lines because the output frequencies from switches 33 and 34 are so high that the shifting between the maximum and minimum potentials of the square waves produced thereby is exceedingly rapid. However, in order to show a particular time period between time 1 and time and the switching that occurs therebetween at time relative to a long time scale, the waveforms of FIG. 3(A), (B), (C), and (D) are illustrated.

On the other hand to more easily understand what transpires during the period between time t, and time t the signal waveforms of FIG. 4(A), (B), (C), and (D), have been presented in an arrangement similar to that illustrated in FIG. 3. Of course, the time scale of FIG. 4 is greatly expanded as compared to the time scale of FIG. 3, thereby allowing the display or portrayal of the actual changing of potentials during the shift periods as depicted in FIG. 4(A), and in FIG. 4(B), as well as in the square wave form signals of FIG. 4(C), and (D). Hence, the waveform of FIG. 4(A) is again shown to be the output from binary counter 24, and the waveform of FIG. 4(B) is shown as being the output waveform from inverter 25 between time 1 and with time I: representing the change of state time of binary counter 24. As a result of said change of state of binary counter 24, the frequency of the signal applied as control signals to bucket brigades l3 and 14 are changed such that the frequencies applied thereto are changed and alternated with respect to each other.

Such change of signal frequencies are ideally represented by the waveforms of FIG. 4(C) and (D), respectively.

As a result of the aforementioned changing of state of binary counter, 24 after every 5 12 bits, and as a result of the changing of the actuation frequencies of bucket brigades l3 and 14 at time t,, the instant of switching, a discontinuity is caused to occur in the output signal from gang switch 35 that is applied to the input of signal processor 38 and thus to, say, earphones 39. However, because the signal waveform of human speech is exceedingly complex, after it has been converted from an acoustical signal into an electrical signal, the pictorial portrayal thereof with any reasonable fidelity is well-nigh impossible, because, obviously, it would vary considerably with the words being spoken. Accordingly, in order to disclose the aforementiond discontinuity and to also disclose that said discontinuity has no adverse effect upon the intelligence communication for most practical purposes, the signal waveforms of FIG. 5(A) and (B) are presented, with FIG. 5(A) thereof being illustrated as a simple sine wave test signal. Therefore, when the waveform of FIG. 5(A) is supplied to an acoustical form to microphone 11, it is converted into the electrical equivalent thereof which is then processed through the 5 12 bit bucket brigade delay lines in accordance with the frequency employed in oscillator l9 and the ratio of the frequencies of clock generators 36 and 37. Of course, as previously indicated, clock generators 36 and 37 are each timely activated as a result of the activation of switches 33 and 34, respectively, which, in turn, are timely and alternately activated as a result of binary counter 24 changing state every bits and the signal output therefrom being applied to the respective NAND gates of switches 33 and 34, along with the inverted version thereof which emanates from inverter 25 which is also applied to the appropriate NAND gates of said switch 33 and 34. The timing of the aforementioned switches 15 and 16 is also effected by binary counter 24 which either directly or indirectly applies the proper voltage to the gates of transistor 17 and 18 in synchronization with the actuation of clock generators 36 and 37, respectively. Consequently, the outputs of bucket brigade delay lines 13 and 14 are alternately supplied through switches 15 and 16 to the input of signal processor 38 for ultimate use within earphone 39, recorder 41, readout 42, or utilization apparatus 43.

The operation of the species of the invention depicted in FIG. 2 is comparable to the operation of the species depicted in FIG. 1, except for the method and means of effecting the switching operation therein. Accordingly, it will only be described very briefly in conjunction with some of the parameters particularly employed therein.

When used as a helium speech decoder, the human speech is picked up by microphone 51 processed and amplified by signal processor 52 and amplifier 53 and then loaded into the two 512 bit bucket brigade delay lines 54 and 55. Said two bucket brigade delay lines are driven by two separate clock generators 73 and 74, respectively, and if the three switches identified as switches 64, 65, and 66 are in the positions shown, then a l00 kilohertz clock signal generated by the oscillator 56 and the output signal from decade counter 59 is applied to bucket brigade delay line 55 to thereby cause it to be loaded with the output of amplifier 53 at a 100 kilohertz rate. Bucket brigade delay line 54 is clocked from the programmable counter 57. The division ratio of this counter is determined externally by inserting a number N by means of a binary coded decimal, two decade switch 58. For the purpose of this explanation, let N be any integer from 10 to 30, although obviously other numbers may be used, if so desired. This means that the clock signal applied by clock generator 73 to bucket brigade delay line 54 is between 100 kilohertz and 33 /3 kilohertz. Of course, it can be seen that, under such circumstances, the ratio of the two clock generators that are applied to the two bucket brigade delay lines lies somewhere between 1.0 and 3.0, such as, for example, 1.0, L1, 1.2 2.9, and 3.0. Bucket brigade delay line 54 is connected, in this instance, through closed switch 65 and through amplifier 76 to the inputs of earphones 77, readout 78, and utilization apparatus 79. Thus, for one-half cycle of the ten stage binary counter, bucket brigade delay line 54 is emptied at a 50 kilohertz rate if N is selected to be 20. Then, after 512 50 kilohertz clock pulses, 10 stage binary counter 25 changes state which, in turn, causes switches 64, 65, and 66 to change position. At such time, the continuity therethrough will be such that bucket brigade delay line 54 will now be loaded at a I 100 kilohertz rate and the bucket brigade delay line 55 will be unloaded at a 50 kilohertz rate through switch 65, through amplifier 76, and into earphone 77, readout 78, and utilization apparatus 79. Of course, after 512 more 50 kilohertz clock pulses occur, binary counter will cause solenoid 62 to change the position of switches 64, 65, and 66, and the process will then be repeated.

The net result of all this is that all voice frequencies above about hertz are divided by N/lO if the abovementioned parameters are employed. All frequencies below 50 hertz will remain unchanged. And, hence, the desired results of helium speech decoding will have been accomplished.

Obviously, the aforementioned values and parameters are exemplary only; therefore, said values and parameters may be selected according to any given requirement or operational circumstance, in order to effect optimum operation of the subject invention. Making the proper selection therefor, would, of course, be well within the purview of one skilled in the art having the benefit of the teachings presented herewith and, accordingly, so doing certainly falls within the scope and spirit of the invention.

Although the waveforms of FIGS. 3, 4, and 5 are also pertinent to the species of the invention of FIG. 2, as far as the specific definition of what occurs therein between time t, and t and t and t it would appear that it would suffice to say that here, again, constitutes the time at which the switching operation of gang switch 61 occurs. And, as a result, signal waveforms of FIG. 4(A), (B), (C), and (D), change as shown in the ideal representation thereof.

From the foregoing, it should readily be seen that the subject invention is a new and unique type of helium speech decoder that produces results that have heretofore been unobtainable by the prior art. Therefore, as disclosed above, the two species of the subject invention set forth in FIGS. 1 and 2 achieve the improved stated objectives mentioned above.

Obviously, other embodiments and modifications of the subject invention will readily come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing description and the drawings. It is, therefore, to be understood that this invention is not to be limited thereto and that said modifications and embodiments are intended to be included within the scope of the appended claims.

What is claimed is:

1. A pitch sealer, comprising in combination:

a first bucket brigade delay line having a loading input, a driving input, and an unloading output; means connected to the driving input of said first bucket brigade delay line for effecting the timely loading and unloading thereof in response to a first signal having a predetermined first frequency; a second bucket brigade delay line having a loading input, a driving input, and an unloading output;

means connected to the driving input of said second bucket brigade delay line for effecting the timely loading and unloading thereof in response to a second signal having a second predetermined fre quency;

means for generating said first signal having said first predetermined frequency;

means for generating said second signal having said second predetermined frequency;

means connected between the output of said first signal generating means and the input of said first bucket brigade delay line loading and unloading effecting means for timely supplying said first signal thereto in effective response to a third signal;

means connected between the output of said second signal generating means and the input of said second bucket brigade delay line loading and unloading effecting means for timely supplying said second signal thereto in effective response to a fourth signal; and

means connected between the output of said first signal generating means and predetermined ones of the inputs of the aforesaid first and second signal generating means for alternately supplying said third and fourth signals thereto for predetermined programmed time periods, respectively.

2. The device of claim 1, further characterized by means connected to the inputs of said first and second bucket brigade delay lines for effecting an electrical connection therebetween that is adapted for being connected to the output of a compatible signal supplying apparatus.

3. The invention of claim 1, further characterized by means respectively connected to the outputs of said first and second bucket brigade delay lines for passing the respective output signals therefrom in respective alternate synchronism with the aforesaid third and fourth signals.

4. The device of claim 1, wherein said first bucket brigade delay line is a 512 bit analog bucket brigade delay line.

5. The device of claim 1, wherein said means connected to the driving input of said first bucket brigade delay line for effecting the timely loading and unloading thereof in response to a first signal having a predetermined first frequency comprises a clock generator.

6. The device of claim 1, wherein said second bucket brigade delay line is a 512 bit analog bucket brigade delay line.

7. The device of claim 1, wherein said means connected to the driving input of said second bucket brigade delay line for effecting the timely loading and unloading thereof in response to a second signal having a predetermined second frequency comprises a clock generator.

8. The device of claim 1, wherein said means for generating said first signal having said first predetermined frequency comprises:

an oscillator;

a programmable counter having a pair of inputs and an output, with one of the inputs thereof connected to the output of said oscillator; and

a binary coded decimal two decade switch connected to the other input of said programmable counter in such manner as to supply a predetermined programming number N thereto.

9. The device of claim 1, wherein said means for generating said second signal having a second predetermined frequency comprises:

an oscillator; and

a decade counter connected to the output of said oscillator.

10. The device of claim 1, wherein said means connected between the output of said first signal generating means and the input of said first bucket brigade delay line loading and unloading effecting means for timely supplying said first signal thereto in effective response to a third signal comprises a switch means.

11. The device of claim 10, wherein said switch means comprises:

a first NAND gate having a pair of inputs and an output;

a second NAND gate having a pair of inputs and an output; and

a third NAND gate having a pair of inputs and an output, with the inputs thereof connected to the outputs of said first and second NAND gates, respectively.

12. The device of claim 10, wherein said switch means comprises a single throw-double pole switch.

13. The device of claim 1, wherein said means connected between the output of said second signal generating means and the input of said second bucket brigade delay line loading and unloading means for timely supplying said second signal thereto in effective response to a fourth signal comprises a switch means.

14. The device of claim 13, wherein said switch means comprises:

a first NAND gate having a pair of inputs and an output;

a second NAND gate having a pair of inputs and an output; and

a third NAND gate having a pair of inputs and an output, with the inputsthereof connected to the outputs of said first and second NAND gates, respec tively.

15. The device of claim 13, wherein said switch means comprises a single throw-double pole switch.

16. The device of claim 1, wherein said means connected between the output of said first signal generating means and predetermined ones of the inputs of the aforesaid first and second signal supplying means for alternately supplying said third and fourth signals thereto for predetermined time periods, respectively, comprises:

a binary counter having an input and an output, with the input thereof connected to the output of said first signal generating means, and the output thereof connected to predetermined ones of the inputs of the aforesaid first and second signal supplying means; and

an inverter having an input and an output, with the input thereof connected to the output of said binary counter, and with the output thereof connected to predetermined other inputs of said first and second signal supplying means.

17. The invention of claim 1, further characterized a microphone;

a first signal processor, including a first amplifier,

connected to the output of said microphone;

means for electrically connecting the output of said signal processor to the inputs of said first and second bucket brigade delay lines;

a second signal processor, including a second amplifier, effectively connected to the outputs of said first and second bucket brigade delay lines; and

a readout connected to the output of the aforesaid second signal processor.

18. A signal sealer, comprising in combination:

a transducer for converting a predetermined parameter into an electrical signal proportional thereto;

a first bucket brigade delay line connected to the output of said transducer;

a first field effect transistor having a drain input, a gate input, and a source output, with the drain input thereof connected to the output of said first bucket brigade delay line;

a second bucket brigade delay line having a data signal input, a shifting input, and an output, with the data signal input thereof effectively connected to the output of the aforesaid transducer;

a second field effect transistor having a drain input, a gate input, and a source output, with the drain input thereof connected to the output of said second bucket brigade delay line;

an adjustable frequency oscillator;

a programmable counter having a data signal input and a plurality of a programming number inputs, with the data signal input thereof connected to the output of the aforesaid oscillator;

a binary coded decimal two-decade switch having a plurality of outputs connected to the programming inputs of said programmable counter for supplying a predetermined programming number thereto;

a decade counter having an input and an output, with the input thereof connected to the output of said adjustable oscillator;

a first clock generator having an input and a pair of outputs, with the outputs thereof connected to the shift inputs of said first bucket brigade delay line;

a fourth NAND gate having a pair of inputs and an output with one of the inputs thereof connected to the gate of said second field effect transistor and one of the inputs of said first NAND gate, with the other input thereof connected to the output of the aforesaid programmable counter and to one of the inputs of said second NAND gate;

a fifth NAND gate having a pair of inputs and an output, with one of the inputs thereof connected to the output of said decade counter and to the other input of said first NAND gate, and with the other input thereof connected to the gate input of said first field effect transistor and the other input of said second NAND gate;

a sixth NAND gate having a pair of inputs and an output, with the pair of inputs thereof respectively connected to the outputs of said fourth and fifth NAND gates, and with the output thereof connected to the input of the aforesaid second clock generator;

a binary counter having an input and an output, with the input thereof connected to the output of the aforesaid programmable counter, and with the output thereof connected to the gate input of said second field effect transistor;

an inverter having an input and an output, with the input thereof connected to the output of said binary counter, and with the output thereof connected to the gate input of the aforesaid first field effect transistor; and

a readout, including earphones and a recorder, effectively connected to the source outputs of the aforesaid first and second field effect transistors.

19. The invention of claim 18, further comprising a utilization apparatus effectively connected to the source outputs of said first and second field effect transistors. 

1. A pitch scaler, comprising in combination: a first bucket brigade delay line having a loading input, a driving input, and an unloading output; means connected to the driving input of said first bucket brigade delay line for effecting the timely loading and unloading thereof in response to a first signal having a predetermined first frequency; a second bucket brigade delay line having a loading input, a driving input, and an unloading output; means connected to the driving input of said second bucket brigade delay line for effecting the timely loading and unloading thereof in response to a second signal having a second predetermined frequency; means for generating said first signal having said first predetermined frequency; means for generating said second signal having said second predetermined frequency; means connected between the output of said first signal generating means and the input of said first bucket brigade delay line loading and unloading effecting means for timely supplying said first signal thereto in effective response to a third signal; means connected between the output of said second signal generating means and the input of said second bucket brigade delay line loading and unloading effecting means for timely supplying said second signal thereto in effective response to a fourth signal; and means connected between the output of said first signal generating means and predetermined ones of the inputs of the aforesaid first and second signal generating means for alternately supplying said third and fourth signals thereto for predetermined programmed time periods, respectively.
 2. The device of claim 1, further characterized by means connected to the inputs of said first and second bucket brigade delay lines for effecting an electrical connection therebetween that is adapted for being connected to the output of a compatible signal supplying apparatus.
 3. The invention of claim 1, further characterized by means respectively connected to the outputs of said first and second bucket brigade delay lines for passing the respective output signals therefrom in respective alternate synchronism with the aforesaid third and fourth signals.
 4. The device of claim 1, wherein said first bucket brigade delay line is a 512 bit analog bucket brigade delay line.
 5. The device of claim 1, wherein said means connected to the driving input of said first bucket brigade delay line for effecting the timely loading and unloading thereof in response to a first signal having a predetermined first frequency comprises a clock generator.
 6. The device of claim 1, wherein said second bucket brigade delay line is a 512 bit analog bucket brigade delay line.
 7. The device of claim 1, wherein said means connected to the driving input of said second bucket brigade delay line for effecting the timely loading and unloading thereof in response to a second signal having a predetermined second frequency comprises a clock generator.
 8. The device of claim 1, wherein said means for generating said first signal having said first predetermined frequency comprises: an oscillator; a programmable counter having a pair of inputs and an output, with one of the inputs thereof connected to the output of said oscillator; and a binary coded decimal two decade switch connected to the other input of said programmable counter in such manner as to supply a predetermined programming number N thereto.
 9. The device of claim 1, wherein said means for generating said second signal having a second predetermined frequency comprises: an oscillator; and a decade counter connected to the output of said oscillator.
 10. The device of claim 1, wherein said means connected between the output of said first signal generating means and the input of said first bucket brigade delay line loading and unloading effecting means for timely supplying said first signal thereto in effective response to a third signal comprises a switch means.
 11. The device of claim 10, wherein said switch means comprises: a first NAND gate having a pair of inputs and an output; a second NAND gate having a pair of inputs and an output; and a third NAND gate having a pair of inputs and an output, with the inputs thereof connected to the outputs of said first and second NAND gates, respectively.
 12. The device of claim 10, wherein said switch means comprises a single throw-double pole switch.
 13. The device of claim 1, wherein said means connected between the output of said second signal generating means and the input of said second bucket brigade delay line loading and unloading means for timely supplying said second signal thereto in effective response to a fourth signal comprises a switch means.
 14. The device of claim 13, wherein said switch means comprises: a first NAND gate having a pair of inputs and an output; a second NAND gate having a pair of inputs and an output; and a third NAND gate having a pair of inputs and an output, with the inputs thereof connected to the outputs of said first and second NAND gates, respectively.
 15. The device of claim 13, wherein said switch means comprises a single throw-double pole switch.
 16. The device of claim 1, wherein said means connected between the output of said first signal generating means and predetermined ones of the inputs of the aforesaid first and second signal supplying means for alternately supplying said third and fourth signals thereto for predetermined time periods, respectively, comprises: a binary counter having an input and an output, with the input thereof connected to the output of said first signal generating means, and the output thereof connected to predetermined ones of the inputs of the aforesaid first and second signal supplying means; and an inverter having an input and an output, with the input thereof connected to the output of said binary counter, and with the output thereof connected to predetermined other inputs of said first and second signal supplying means.
 17. The invention of claim 1, further characterized by: a microphone; a first signal processor, including a first amplifier, connected to the output of said microphone; means for electrically connecting the output of said signal processor to the inputs of said first and second bucket brigade delay lines; a second signal processor, including a second amplifier, effectively connected to the outputs of said first and second bucket brigade delay lines; and a readout connected to the output of the aforesaid second signal processor.
 18. A signal scaler, comprising in combination: a transducer for converting a predetermined parameter into an electrical signal proportional thereto; a first bucket brigade delay line connected to the output of said transducer; a first field effect transistor having a drain input, a gate input, and a source output, with the drain input thereof connected to the output of said first bucket brigade delay line; a second bucket brigade delay line having a data signal input, a shifting input, and an output, with the data signal input thereof effectively connected to the output of the aforesaid transducer; a second field effect transistor having a drain input, a gate input, and a source output, with the drain input thereof connected to the output of said second bucket brigade delay line; an adjustable frequency oscillator; a programmable counter having a data signal input and a plurality of a programming number inputs, with the data signal input thereof connected to the output of the aforesaid oscillator; a binary coded decimal two-decade switch having a plurality of outputs connected to the programming inputs of said programmable counter for supplying a predetermined programming number thereto; a decade counter having an input and an output, with the input thereof connected to the output of said adjustable oscillator; a first clock generator having an input and a pair of outputs, with the outputs thereof connected to the shift inputs of said first bucket brigade delay line; a second clock generator having an input and a pair of outputs, with the outputs thereof connected to the shift inputs of said second bucket brigade delay line; a first NAND gate having a pair of inputs and an output; a second NAND gate having a pair of inputs and an output; a third NAND gate having a pair of inputs and an output, with the pair of inputs thereof respectively connected to the outputs of the aforesaid first and second NAND gates, and with the output thereof connected to the input of said first clock generator; a fourth NAND gate having a pair of inputs and an output with one of the inputs thereof connected to the gate of said second field effect transistor and one of the inputs of said first NAND gate, with the other input thereof connected to the output of the aforesaid programmable counter and to one of the inputs of said second NAND gate; a fifth NAND gate having a pair of inputs and an output, with one of the inputs thereof connected to the output of said decade counter and to the other input of said first NAND gate, and with the other input thereof connected to the gate input of said first field effect transistor and the other input of said second NAND gate; a sixth NAND gate having a pair of inputs and an output, with the pair of inputs thereof respectively connected to the outputs of said fourth and fifth NAND gates, and with the output thereof connected to the input of the aforesaid second clock generator; a binary counter having an input and an output, with the input thereof connected to the output of the aforesaid programmable counter, and with the output thereof connected to the gate input of said second field effect transistor; an inverter having an input and an output, with the input thereof connected to the output of said binary counter, and with the output thereof connected to the gate input of the aforesaid first field effect transistor; and a readout, including earphones and a recorder, effectively connected to the source outputs of the aforesaid first and second field effect transistors.
 19. The invention of claim 18, further comprising a utilization apparatus effectively connected to the source outputs of said first and second field effect transistors. 